verilog code for bcd to binary
verilog code for bcd to binary BCD TO BINARY module bcd2binary ( input [ 7 : 0 ] bcd , output reg [ 3 : 0 ] binary) ; always @( bcd ) begin if (bcd [ 3 : 0 ] < 4b1010 ) begin if (bcd [ 7 : 4 ] = = { 4 { 1b0 } } ) binary = bcd [ 3 : 0 ] ; if ((bcd [ 7 : 5 ] = = { 3 { 1b0 } } ) & & (bcd [4] = = 1b1 )) binary = bcd [ 3 : 0 ] + 4b1010 ; end else binary = { 4 { 1bx } } ; end endmodule TEST BENCH module bcd2binary_tb ; reg [ 7 : 0 ] bcd ; wire [ 3 : 0 ] binary ; bcd2binary b1 ( bcd , binary ) ; initial begin bcd = 8b00000000 ; $monitor($time , , "bcd" , , "%b" , bcd , , "bin" , "ary" , , "%b" , binary) ; end always # 1 bcd = bcd + 1 ; initial # 22 $stop ; endmodule You can also check more verilog code on http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html download file now