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verilog code for washing machine hello guys.... i am providing u a verilog code for washing machine with testbench.... WASHING MACHINE module wm ( clk , rst , coin , lid_r , d_wash , T , soak , rinse , spin , wash , pause , break ) ; input clk , rst , coin , lid_r , d_wash , T ; output reg soak , rinse , spin , wash , pause , break ; reg [ 2 : 0 ] cst , nst ; // state assignment parameter IDLE = 3b000 , SOAK = 3b001 , WASH = 3b010 , RINSE = 3b011 , WASH2 = 3b100 , RINSE2 = 3b101 , SPIN = 3b110 , PAUSH = 3b111 ; always @( cst or coin or d_wash or lid_r or T ) begin case ( cst ) IDLE : if ( coin== 1 ) begin nst=SOAK ; soak= 1 ; rinse= 0 ; spin= 0 ; wash= 0 ; pause= 0 ; break= 0 ; end else begin nst=cst ; soak= 0 ; rinse= 0 ; spin= 0 ; wash= 0 ; pause= 0 ; break= 0 ; end SOAK : if ( T== 1 ) begin nst=WASH ; soak= 0 ; rinse= 0 ; spin= 0 ; wash= 1 ; pause= 0 ; break= 0 ; end else begin nst=cst ; soak= 1 ; rinse= 0 ; spin= 0 ; was...

verilog code for bcd to binary BCD TO BINARY module bcd2binary ( input [ 7 : 0 ] bcd , output reg [ 3 : 0 ] binary) ; always @( bcd ) begin if (bcd [ 3 : 0 ] < 4b1010 ) begin if (bcd [ 7 : 4 ] = = { 4 { 1b0 } } ) binary = bcd [ 3 : 0 ] ; if ((bcd [ 7 : 5 ] = = { 3 { 1b0 } } ) & & (bcd [4] = = 1b1 )) binary = bcd [ 3 : 0 ] + 4b1010 ; end else binary = { 4 { 1bx } } ; end endmodule TEST BENCH module bcd2binary_tb ; reg [ 7 : 0 ] bcd ; wire [ 3 : 0 ] binary ; bcd2binary b1 ( bcd , binary ) ; initial begin bcd = 8b00000000 ; $monitor($time , , "bcd" , , "%b" , bcd , , "bin" , "ary" , , "%b" , binary) ; end always # 1 bcd = bcd + 1 ; initial # 22 $stop ; endmodule You can also check more verilog code on http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html download  file  now

verilog code for counter COUNTER INCREMENT BY 2 module counter2 ( r , clk , y ) ; input r , clk ; output [ 3 : 0 ] y ; reg [ 3 : 0 ] y ; always @( posedge clk or posedge r ) begin if (r) y < = 4b0000 ; else y < = y + 2 ; end endmodule TESTBENCH module counter3_tb ; reg r , clk ; wire [ 3 : 0 ] y ; counter2 m1 ( r , clk , y ) ; initial begin clk = 0 ; r = 0 ; $monitor($time , , , "c = %b" , clk , , "r = %b" , r , , "y = %b" , y) ; # 5 r = 1 ; # 15 r = 0 ; # 50 $finish ; end always begin # 5 clk = ~ clk ; end endmodule OUTPUT � COUNTER INCREMENT BY 3 module counter2 ( r , clk , y ) ; input r , clk ; output [ 3 : 0 ] y ; reg [ 3 : 0 ] y ; always @( posedge clk or posedge r ) begin if (r) y < = 4b0000 ; else y < = y + 3 ; end endmodule TESTBENCH module counter3_tb ; reg r , clk ; wire [ 3 : 0 ] y ; counter2 m1 ( r , clk , y ) ; initial begin clk = 0 ; r = 0 ; $monitor($time , , , "c = %b" , clk , , "r = %b...

verilog code for 4 bit ripple carry adder using full adder 4 - BIT RIPPLE CARRY ADDER USING FULL ADDER module rip2 ( s , cout , a , b , cin ) ; input [ 3 : 0 ] a ; input [ 3 : 0 ] b ; input cin ; output cout ; output [ 3 : 0 ] s ; wire c2 , c3 , c4 , cout ; fa m1 ( s [0] , c2 , a [0] , b [0] , cin ) ; fa m2 ( s [1] , c3 , a [1] , b [1] , c2 ) ; fa m3 ( s [2] , c4 , a [2] , b [2] , c3 ) ; fa m4 ( s [3] , cout , a [3] , b [3] , c4 ) ; endmodule TESTBENCH module fa ( s , cout , a , b , cin ) ; input a , b , cin ; output s , cout ; wire w1 , w2 , w3 ; ha m1 ( w1 , w2 , a , b ) ; ha m2 ( s , w3 , w1 , cin ) ; or m3 ( cout , w2 , w3 ) ; endmodule module ha ( s , cout , a , b ) ; //sub module for Half adder input a , b ; output s , cout ; xor m1 ( s , a , b ) ; and m2 ( cout , a , b ) ; endmodule module rip2_tb ; reg [ 3 : 0 ] a ; reg [ 3 : 0 ] b ; reg cin ; wire cout ; wire [ 3 : 0 ] s ; rip2 m1 ( s , cout , a , b , cin ) ; initial begin a = 4b0000 ; b = 4b00...

verilog code for mejority detector MEJORITY DETECTOR module majority ( input v1 , v2 , v3 , output reg m) ; always @( v1 or v2 or v3 ) begin if ((v1 & & v2) | (v2 & & v3) | (v3 & & v1)) m = 1 ; else m = 0 ; end endmodule TESTBENCH module majority_tb ; reg v1 , v2 , v3 ; wire m ; majority m1 ( v1 , v2 , v3 , m ) ; initial begin v1 = 0 ; v2 = 0 ; v3 = 0 ; $monitor($time , , , v1 , v2 , v3 , , "m = %d" , m) ; # 2 v1 = 0 ; v2 = 0 ; v3 = 0 ; # 2 v1 = 0 ; v2 = 0 ; v3 = 1 ; # 2 v1 = 0 ; v2 = 1 ; v3 = 1 ; # 2 v1 = 1 ; v2 = 0 ; v3 = 0 ; # 2 v1 = 1 ; v2 = 0 ; v3 = 1 ; # 2 v1 = 1 ; v2 = 1 ; v3 = 0 ; # 2 v1 = 1 ; v2 = 1 ; v3 = 1 ; end endmodule You can also check more verilog code on http://kaneriadhaval.blogspot.in/2013/11/all-besic-verilog-code.html download  file  now

verilog code for 16x2 mux using 2x1 16x2 MUX USING 2X1 MUX USING STRUCTRAL MODELING module mux16to1 ( input [ 15 : 0 ] w , input [ 3 : 0 ] s , output wire [ 15 : 0 ] m , output f) ; mux2to1 mu1 ( m [0] , w [ 1 : 0 ] , s [0] ) ; mux2to1 mu2 ( m [1] , w [ 3 : 2 ] , s [0] ) ; mux2to1 mu3 ( m [2] , w [ 5 : 4 ] , s [0] ) ; mux2to1 mu4 ( m [3] , w [ 7 : 6 ] , s [0] ) ; mux2to1 mu5 ( m [4] , w [ 9 : 8 ] , s [0] ) ; mux2to1 mu6 ( m [5] , w [ 11 : 10 ] , s [0] ) ; mux2to1 mu7 ( m [6] , w [ 13 : 12 ] , s [0] ) ; mux2to1 mu8 ( m [7] , w [ 15 : 14 ] , s [0] ) ; mux2to1 mu9 ( m [8] , m [ 1 : 0 ] , s [1] ) ; mux2to1 mu10 ( m [9] , m [ 3 : 2 ] , s [1] ) ; mux2to1 mu11 ( m [10] , m [ 5 : 4 ] , s [1] ) ; mux2to1 mu12 ( m [11] , m [ 7 : 6 ] , s [1] ) ; mux2to1 mu13 ( m [12] , m [ 9 : 8 ] , s [2] ) ; mux2to1 mu14 ( m [13] , m [ 11 : 10 ] , s [2] ) ; mux2to1 mu15 ( f , m [ 13 : 12 ] , s [3] ) ; endmodule module mux2to1 ( output f , input [ 1 : 0 ] w , sel ) ; and m1 ( x , w [0] , ~ sel ) ; and m2 ( y , ...

verilog code for D flip flop sync reset Verilog code For D flip-flop sync reset module dff_sync_reset ( data , // Data Input clk , // Clock Input reset , // Reset input q // Q output ); //-----------Input Ports--------------- input data, clk, reset ; //-----------Output Ports--------------- output q; //------------Internal Variables-------- reg q; //-------------Code Starts Here--------- always @ ( posedge clk) if (~reset) begin q <= 1b0; end else begin q <= data; end endmodule //End Of Module dff_sync_reset download  file  now

verilog code for D flip flop async reset Verilog code for D flip-flop async reset module dff_async_reset ( data , // Data Input clk , // Clock Input reset , // Reset input q // Q output ); //-----------Input Ports--------------- input data, clk, reset ; //-----------Output Ports--------------- output q; //------------Internal Variables-------- reg q; //-------------Code Starts Here--------- always @ ( posedge clk or negedge reset) if (~reset) begin q <= 1b0; end else begin q <= data; end endmodule //End Of Module dff_async_reset VERILOG CODE FOR D flip-flop sync reset download  file  now

verilog code for candy vending machine hello friends.... I a m providing u verilog code for candy vending machine with test bench. CANDY MACHINE module candy ( d , n , q , reset , clk , y ) ; output reg y ; input d , n , q ; //n=5,d=10,q=25; input clk ; input reset ; reg [ 2 : 0 ] cst , nst ; parameter S0 = 3b000 , S1 = 3b001 , S2 = 3b010 , S3 = 3b100 , S4 = 3b101 , S5 = 3b110 , S6 = 3b111 ; always @( cst or d or n or q ) begin case ( cst ) S0 : if ( n== 1b1 && d== 1b0 && q== 1b0 ) begin nst = S1 ; y= 1b0 ; end else if ( n== 1b0 && d== 1b1 && q== 1b0 ) begin nst=S2 ; y= 1b0 ; end else if ( n== 1b0 && d== 1b0 && q== 1b1 ) begin nst=S5 ; y= 1b0 ; end else begin nst = cst ; y= 1b0 ; end S1 : if ( n== 1b1 && d== 1b0 && q== 1b0 ) begin nst = S2 ; y= 1b0 ; end else if ( n== 1b0 && d== 1b1 && q== 1b0 ) begin nst=S3 ; y= 1b0 ; end else if ( n=...