verilog code for washing machine hello guys.... i am providing u a verilog code for washing machine with testbench.... WASHING MACHINE module wm ( clk , rst , coin , lid_r , d_wash , T , soak , rinse , spin , wash , pause , break ) ; input clk , rst , coin , lid_r , d_wash , T ; output reg soak , rinse , spin , wash , pause , break ; reg [ 2 : 0 ] cst , nst ; // state assignment parameter IDLE = 3b000 , SOAK = 3b001 , WASH = 3b010 , RINSE = 3b011 , WASH2 = 3b100 , RINSE2 = 3b101 , SPIN = 3b110 , PAUSH = 3b111 ; always @( cst or coin or d_wash or lid_r or T ) begin case ( cst ) IDLE : if ( coin== 1 ) begin nst=SOAK ; soak= 1 ; rinse= 0 ; spin= 0 ; wash= 0 ; pause= 0 ; break= 0 ; end else begin nst=cst ; soak= 0 ; rinse= 0 ; spin= 0 ; wash= 0 ; pause= 0 ; break= 0 ; end SOAK : if ( T== 1 ) begin nst=WASH ; soak= 0 ; rinse= 0 ; spin= 0 ; wash= 1 ; pause= 0 ; break= 0 ; end else begin nst=cst ; soak= 1 ; rinse= 0 ; spin= 0 ; was