verilog code for washing machine

verilog code for washing machine

hello guys....

i am providing u a verilog code for washing machine with testbench....

WASHING MACHINE

module wm(clk,rst,coin, lid_r, d_wash, T, soak,rinse, spin, wash,pause,break);
 input clk,rst,coin,lid_r,d_wash,T;
 output reg soak,rinse,spin,wash,pause,break;
 reg[2:0] cst, nst;

 // state assignment
 parameter IDLE = 3b000,
 SOAK = 3b001,
 WASH=3b010,
 RINSE=3b011,
 WASH2=3b100,
 RINSE2=3b101,
 SPIN=3b110,
 PAUSH=3b111;

always @(cst or coin or d_wash or lid_r or T)
begin
 case (cst)
 IDLE:
if(coin==1)
 begin
 nst=SOAK;
 soak=1;
 rinse=0;
 spin=0;
 wash=0;
 pause=0;
 break=0;
 end
else

 begin
 nst=cst;
 soak=0;
 rinse=0;
 spin=0;
 wash=0;
 pause=0;
 break=0;
 end

SOAK:
if(T==1)

 begin
 nst=WASH;
 soak=0;
 rinse=0;
 spin=0;
 wash=1;
 pause=0;
 break=0;
 end
else
 begin
 nst=cst;
 soak=1;
 rinse=0;
 spin=0;
 wash=0;
 pause=0;
 break=0;
 end
 WASH:
if(T==1)

 begin
 nst=RINSE;
 soak=0;
 rinse=1;
 spin=0;
 wash=0;
 pause=0;
 break=0;
 end
else
 begin
 nst=cst;
 soak=0;
 rinse=0;
 spin=0;
 wash=1;
 pause=0;
 break=0;
 end
RINSE:
if(T==1 && d_wash==1)

 begin
 nst=WASH2;
 soak=0;
 rinse=0;
 spin=0;
 wash=1;
 pause=0;
 break=0;
 end
else if(T==1 && d_wash==0)

 begin
 nst=SPIN;
 soak=0;
 rinse=0;
 spin=1;
 wash=0;
 pause=0;
 break=0;
 end
else
 begin
 nst=cst;
 soak=0;
 rinse=1;
 spin=0;
 wash=0;
 pause=0;
 break=0;
 end
WASH2:
if(T==1)

 begin
 nst=RINSE2;
 soak=0;
 rinse=1;
 spin=0;
 wash=0;
 pause=0;
 break=0;
 end
else
 begin
 nst=cst;
 soak=0;
 rinse=0;
 spin=0;
 wash=1;
 pause=0;
 break=0;
 end

RINSE2:
if(T==1)
 begin
 nst=SPIN;
 soak=0;
 rinse=0;
 spin=1;
 wash=0;
 pause=0;
 break=0;
 end
else
 begin
 nst=cst;
 soak=0;
 rinse=1;
 spin=0;
 wash=0;
 pause=0;
 break=0;
 end
SPIN:
if(T==0 && lid_r==1)
 begin
 nst=PAUSH;
 soak=0;
 rinse=0;
 spin=0;
 wash=0;
 pause=1;
 break=0;
 end
else if(T==1)
 begin
 nst=IDLE;
 soak=0;
 rinse=0;
 spin=0;
 wash=0;
 pause=0;
 break=0;
 end
else
 begin
 nst=cst;
 soak=0;
 rinse=0;
 spin=1;
 wash=0;
 pause=0;
 break=0;
 end
PAUSH:
if(lid_r==0)
 begin
 nst=SPIN;
 soak=0;
 rinse=0;
 spin=1;
 wash=0;
 pause=0;
 break=0;
 end
else
 begin
 nst=cst;
 soak=0;
 rinse=0;
 spin=0;
 wash=0;
 pause=1;
 break=0;
 end
 default:
nst=IDLE;
 endcase
 end
always @(posedge clk or negedge rst)
begin
 if (rst)
 cst <= IDLE;
 else
 cst <= nst;
 end
/*
  assign soak = (cst == SOAK);
  assign rinse = (cst == RINSE) | (cst == RINSE2);
  assign brake = (cst == PAUSE);
  assign spin = (cst == SPIN);
  assign wash = (cst == WASH) | (cst == WASH2);
*/
endmodule

TEST BENCH

module wm_tb;
reg clk,reset,coin,lid_r,d_wash,T;
wire soak,rinse,spin,wash,pause,break;
wm m1(clk,reset,coin,lid_r,d_wash,T,soak,rinse,spin,wash,pause,break);
initial
begin

$monitor($time, ,,"c=%b",clk,,"t=%b",coin,,"l=%b",lid_r,,"d=%b",d_wash,,"T=%b",T,,"s=%b",soak,,"r=%b",rinse,,"S=%b",spin,,"w=%b",wash,,"p=%b",pause,,"b=%b",break);
reset=0 ;clk=0;coin=0;lid_r=0;d_wash=0;T=0;
#10 coin=1;
#10 T=1;coin=0;
#20 d_wash=1;
#30 lid_r=1;d_wash=0;T=0;
#10 lid_r=0;T=0;
#10 T=1;lid_r=0;
#10 T=1;
#10 coin=1;T=0;
//#10 T=1;
//#10 T=1;
//#5 reset=1;
//#5 reset=0;
end
always
#5 clk=~clk;
initial
#100 $finish ;

endmodule

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