verilog code for D flip flop sync reset

verilog code for D flip flop sync reset

Verilog code For D flip-flop sync reset

module dff_sync_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset ; 

//-----------Output Ports---------------
output q;

//------------Internal Variables--------
reg q;

//-------------Code Starts Here---------
always @ ( posedge clk)
if (~reset) begin
 q <= 1b0;
end else begin
 q <= data;
end

endmodule //End Of Module dff_sync_reset

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